1. Field of the Invention
This invention relates to a solid-state imaging device for use in a television camera, etc. Particularly, it relates to a solid-state imaging device which has a plurality of picture elements disposed linearly or areally in a surface region of a semiconductor body. More specifically, it relates to a signal read-out circuit in the solid-state imaging device which has picture elements for reading out from photoelectric conversion elements photo information detected therein.
2. Description of the Prior Art
As a prior-art solid-state imaging device, there is one as shown by way of example in FIG. 1A.
FIG. 1A exemplifies the principle construction of a solid-state area sensor (imaging device), while FIG. 1B shows scanning pulses. In FIG. 1A, numerals 1 and 2 designate horizontal and vertical scanning circuits respectively. Usually, by applying clock pulses CP.sub.x and CP.sub.y in 2-4 phases, the scanning circuits 1 and 2 provide output lines 7 and 8 of their respective stages, that is, O.sub.x(1), O.sub.x(2) . . . and O.sub.y(1), O.sub.y(2) . . . with output pulses V.sub.ox(1), V.sub.ox(2) . . . and V.sub.oy(1), Y.sub.oy(2) . . . in which input pulses V.sub.sx and V.sub.sy have shifted by fixed timing intervals of the clocks. Using the scanning pulses, switching elements 5 and 6 are turned "on" and "off" one by one, to take out to a video output terminal 4 signals from individual photoelectric conversion elements 3 areally arrayed. Since the signals from the photoelectric conversion elements correspond to an optical image of an object projected thereon, video signals can be derived from the output end OUT (4) by the above operation.
In the solid-state imaging device of this type, in order to attain a high resolution, there are required about 500.times.500 photoelectric conversion elements and switching elements and scanning circuits each having a plurality of stages. To this end, the imaging device is ordinarily fabricated by the use of an integrated circuit technology (MOS-LSI technology) employing insulated-gate field effect transistors (MOS transistors) which can be highly integrated comparatively easily and in which a photoelectric conversion element and a switching element can be formed in an integral structure. FIG. 2 shows the structure of the photoelectric conversion element and the switching element which occupy most of the area of the sensor IC. Numeral 13 designates a semiconductor (Si or the like) body (semiconductor substrate, epitaxially grown layer, well diffused region, or the like). Numerals 5 and 6 indicate insulated-gate field effect transistors (MOS transistors) for addressing horizontal and vertical positions. They are made up of diffused layers 14, 15 and 16 forming their drains and sources and having a conductivity type opposite to that of the body, and gate electrodes 18 and 19 disposed through an insulating film (SiO.sub.2 or the like). The source 14 of the vertical switching MOS transistor is utilized as a photodiode. The combination of the photodiode 14 and the vertical switching MOS transistor 6 is called the "picture element". When output pulses V.sub.ox(N) and V.sub.oy(N) from scanning circuits 1 and 2 utilizing, for example, shift registers constructed of MOS transistors are simultaneously applied to the gates of the switching MOS transistors through scanning lines O.sub.x(N) and O.sub.y(N), charges in a quantity having been discharged from the diode 14 at the addressed position in proportion to incident photons are charged from a voltage source for a video output 11. The charging current at that time is read out as a video signal from an output terminal OUT (4) through a load resistance 12.
In such prior-art device, however, a fixed pattern noise (abbreviated to "FPN") occurs by a cause to be stated below, and it is a fatal drawback.
FIG. 3A depicts the structure of FIG. 2 more simply. A part 13 is, for example, a Si body of the P-type conductivity, and a part 14 is one photodiode which is made of a diffusion layer of the N.sup.+ -type conductivity. A part 16 in FIG. 3A corresponds to the horizontal signal output line 10 shown in FIG. 1A, while a part 15 corresponds to the vertical signal output line 9 shown in FIG. 1A. The part 15 in FIG. 3A may well be separated into the two regions of the drain of a MOS transistor 6 and the source of a MOS transistor 5, the respective regions being connected by a metal such as aluminum.
FIGS. 3B to 3F illustrate channel potentials corresponding to FIG. 3A. Now that an N-channel type element is considered, the positive sense of the potential is downward.
In FIG. 3B, signal charges 31 are stored in the photodiode 14, and zero V is applied to the gate 18 of the vertical switching MOS transistor (hereinbelow, simply written "VTr") 6 and the gate 19 of the horizontal switching MOS transistor (hereinbelow, simply written "HTr") 5, so that both the transistors turn "off".
FIG. 3C shows the state in which the VTr 6 turns "on" and the signal charges spread under the gate 18 of the VTr 6 as well as in the vertical signal output line 15. FIG. 3D shows the potential at the time when also the HTr 5 turns "on" and the signal charges are spreading and delivering also to the horizontal signal output line 16. FIG. 3E shows the state in which the signal charges have been once read out and the respective potentials are reset to the video voltage V.sub.o. In FIG. 3F, the HTr 5 turns "off" and a signal of the next picture element is being read out.
As seen from FIGS. 3E and 3F, some 32 of the signal charges are left behind under the gate 19 of the horizontal switching MOS transistor HTr 5, and they are delivered to the horizontal signal output line 16 from under the gate when the horizontal scanning pulse turns "off".
FIG. 4A shows an example of a shift register composed of inverters 41 and transfer MOS transistors 42 and having heretofore been known well, the shift register being a prior-art example of the horizontal scanning circuit.
As illustrated by a pulse timing chart in FIG. 4B, in the prior-art device, the time at which the n-th horizontal scanning pulse V.sub.ox(n) turns "off" and the time at which the succeeding (n+1)-th horizontal scanning pulse V.sub.ox(n+1) turns "on" are determined by the same trigger pulse of the horizontal clock pulse .phi..sub.x2.
More specifically, the time when the horizontal scanning pulse V.sub.ox(n+1) turns "on" is the time when the signal of the (n+1)-th column is provided. Simultaneously, it is the time when the horizontal scanning pulse V.sub.ox(n) of the n-th column turns "off". In short, in the prior-art example, as apparent from FIGS. 3E and 3F, when the signal of the photodiode of the (n+1)-th column is provided, some Q.sub.R 32 of the signal charges of the n-th column having been trapped under the gate 19 of the horizontal switching MOS transistor 5 of the n-th column are provided. If the residual charges Q.sub.R are equal in all the columns, there will be no problem, but when they are unequal, they form one cause for the fixed pattern noise.
As a result, normal video signals cannot be obtained in the solid-state imaging device, and vertical stripes appear on a reproduced picture screen and spoil the picture quality seriously.